1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and, more particularly, to a chip-stacked type semiconductor package and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of science and technologies, electronic products are developed towards miniaturization, multi-function, high electrical performance and high speed. To meet the trend, semiconductor packages are required to have minimized size, high performance and high speed.
According to a fabrication method of a semiconductor package as disclosed by U.S. Pat. No. 5,202,754 and No. 5,270,261, a wafer having an etch stop layer embedded therein is provided and bonded to a carrier. Then, the wafer is thinned by etching until the etch stop layer is exposed. Further, a plurality of through-silicon vias (TSV) are formed in the wafer, and conductive through holes are formed in the TSVs, respectively. Thereafter, the wafer is debonded from the carrier and singulated into a plurality of thinned semiconductor chips. Further, the semiconductor chips can be stacked to form a 3D-IC package having small size and high performance.
However, when the wafer is debonded from the carrier, the wafer can be easily cracked due to its reduced thickness. Further, the bonding and debonding processes can easily cause cracking or damage of the wafer. Furthermore, since the conventional method bonds the entire wafer instead of known good dies to the carrier, the overall fabrication cost is increased. In addition, warpage can easily occur to the thinned wafer, thus adversely affecting subsequent bonding processes.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.